SUPER MICRO Computer X7DVL-3 - Manual (Page 68)

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X7DVL-3/X7DVL-i User's Manual
Branch 0 Rank Interleaving
Select enable to enable the functions of Memory Interleaving for Branch 0 Rank.
The options for Memory Interleaving are 1:1, 2:1 and 4:1.
Branch 0 Rank Sparing
Select enable to enable the sparing feature for Branch 0 Rank. The options are
Enabled and Disabled.
Enhanced x8 Detection
Select Enabled to enable Enhanced x8 DRAM UC Error Detection. The options
are Disabled and Enabled.
High Temperature DRAM Operation
When set to Enabled, the BIOS will refer to the SPD table to set the maximum
DRAM temperature. If disabled, the BIOS will set the maximum DRAM temperature
based on a predefi ned value. The options are Enabled and Disabled.
AMB Thermal Sensor
Select Enabled to enable the thermal sensor embedded in Advanced Memory
Buffer on a fully buffered memory module for thermal monitoring. The options are
Disabled and Enabled.
Thermal Throttle
Select Enabled to enable the function of closed-loop thermal throttling on the fully
buffered (FBD) memory modules. In the closed-loop thermal environment, thermal
throttling will be activated when the temperature of the FBD DIMM device exceeds
a predefi ned threshold. The options are Enabled and Disabled.
Global Activation Throttle
Select Enabled to enable the function of open-loop global thermal throttling on the
fully buffered (FBD) memory modules and allow global thermal throttling to become
active when the number of activate controls exceed a predefi ned number. The
options are Enabled and Disabled.
Snoop Filter
Select Enabled to eliminate snoop traffi c to the graphics port to greatly improve
system performance when running graphics intensive applications. The options are
Enabled and Disabled.
Crystal Beach Features
This feature cooperates with the Intel I/O AT (Acceleration Technology) to accelerate
the performance of TOE devices. (*Note: A TOE device is a specialized, dedicated
processor that is installed on an add-on card or a network card to handle some or all
packet processing of this add-on card. For this motherboard, the TOE device is built
inside the ESB 2 South Bridge chip.) The options are Enabled and Disabled.