Rainbow Electronics U6820BM - Manual (Page 3)

3
U6820BM
4527A–BCD–03/02
Description of the
Control Interface to
the Microcontroller
The serial-parallel interface basically includes an 8-bit shift register (SR), an 8-bit com-
mand register (CR) and a 4-bit counter.
The data input takes place with commands at Pins DI (data input), CS (chip select) and
CLK (clock). With a falling edge at CLK, the information at DI is transferred into the SR.
The first information written into the SR is the least significant bit (LSB). The Pin STA-
TUS is used for diagnostic purposes and reports any fault condition to the
microcontroller.
The input CS in accordance with the CR controls the serial interface. A high level at CS
disables the SR. With a falling edge at CS, the SR is enabled. The CR control allows
only the first 8 bits to be transferred into the SR, and further clocks at CLK are ineffec-
tive. If a rising edge occurs at CS after 8 clocks precisely, the information from the SR is
transferred into the CR. If the number of clock cycles during the low phase of CS was
less or more than eight transitions, no transfer will take place. A new command switches
the output stages on or off immediately.
Each output stage is controlled by one specific bit of the CR. Low level means “supply
off” or inactive, and high level means “supply on” or active. If all 8 bits are at a low level,
the output stages will be set into standby mode.
If one of the output stages detects a short circuit and additionally overtemperature con-
dition, the corresponding control bit in the CR is set to low. This reset has priority over
an external command to CR, thus, this does not affect the 1
st control bit. The priority pro-
tects the IC against overtemperature by activating the temperature shut down
immediately.
The STATUS Output
The STATUS output is at low level during normal operation. If one or more output stages
detect short circuit or if overtemperature is indicated, the STATUS output changes to
high level (OR-connection).
For diagnostic purposes (self test of the status output), the status output can also be
brought into high level during standby mode.
Timing of the Status
Output Reset Signalizes
the Failure Mode The use of different reset conditions at the STATUS output simplifies the failure analysis
during normal operation, and is also beneficial during testing.
The storage content can be used for STATUS output. It is indicated and latched immedi-
ately with the rising edge of CS at STATUS output if less than 8 clocks were received
during the low phase of CS. The reset is initiated by the falling edge of the 8
th clock
(bit 7) of the next data input.
Also, the appearance of more than 8 clocks is latched and indicated at STATUS by the
rising edge of the 9
th clock. The reset is initiated by the falling edge of the 2 nd clock
(bit 1) of the next data input.
The detection of overtemperature is latched internally. It is reset by the falling edge of
the 4
th clock (bit 3) of a data transfer if overtemperature is no longer present.
Power-on Reset After switching on the supply voltage, all data latches are reset and the outputs are
switched off. The typical power-on reset threshold is V
CC
= 3.7 V. The outputs are acti-
vated after the first data transfer.